ITTC Project

DSP Radio Algorithm Development with Field Programmable Gate Arrays

Project Award Date: 0000-00-00


Previous research efforts with Rome Laboratories have led to the development of a digital signal processing rapid prototyping system consisting of Cadence Systems Signal Processing Worksystems (SPW), and Synopsys software tools, with algorithms implemented on FPGAs and paralled-DSP processors. With this system we developed and tested radio algorithms for the Air Force's "Smart Radio" program. With the use of FPGAs, we are investigating ways to speed up the radio algorithms and reduce the signal processing tasks required of the DASP processor.

An essential requirement in military communications is extraction of interference from the received signal as early in the detection process as possible. Military radio systems employ spread spectrum techniques which produce extremely wide bandwidth signals. In order to excise interference at spread spectrum bandwidths, high speed digital signal processing is required. The processing sprrds needed for interference excision at the spread bandwidth normally exceed those available in traditional DSP microporcessors. Therfore we are investigating the implementation of certain interference excision algoithms using FPGA technology to facilitate the rapid (and possibly adaptive) excision of narrow band interferers within a large operating bandwidth.

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Project Sponsors

Primary Sponsor(s): U.S. Air Force Rome Laboratories

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