Automatic Synthesis of Hardware Features to Augment the POWER Architecture
Project Award Date: 01-20-2005
While many SoC and AS P projects are based on paper designs or prohibitively expensive processes, we have the extraordinary benefit that our work can be deployed immediately on commercially available PowerPC hybrid CPUIFPGA development boards. Specifically, we have prior experience working with the Virtex II Pro which has a Power C 405 core with an array of FPGA configurable logic blocks around it. We routinely use IBM's CoreConnect technology to build systems for these devices. under this project, and as part of our long-term focus on run-time reconfigurable architectures, we will develop a tool that can extract a viable subroutine from object code, synthesize a hardware module from it, and replace the subroutine in the original object code with a stub that invokes the module. Our criterion for success is to demonstrate this on a Virtex n Pro. Our long-term goal (year two and beyond) is to incorporate this tool into our run-time system work that dynamically select and reconfigure the POWER architecture's set of hardware features.
Primary Sponsor(s): IBM